EZ80F91MCU Datasheet, PDF (293/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
274
Table 169. EMAC Receive Read Pointer Register—High Byte
(EMAC_RRP_H = 004Ah)
Bit
7
6
Reset
0
0
CPU Access
R
R
Note: R = Read Only, R/W = Read/Write
5
4
3
2
0
0
0
0
R R/W R/W R/W
1
0
R/W
0
0
R/W
Bit
Position
Value
[7:0]
00h–
EMAC_RRP_ FFh
H
Description
These bits represent the High byte of the 2-byte EMAC
Receive Read Pointer value, {EMAC_RRP_H,
EMAC_RRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit 0
is bit 8 of the 16-bit value.
EMAC Buffer Size Register
The lower six bits of this register set the level at which the EMAC either transmits
a pause control frame or jams the Ethernet bus, depending on the mode selected.
When these bits each contain a zero, this feature is disabled.
In Full Duplex Mode, a Pause Control Frame is transmitted as a one-shot opera-
tion. The software must free up a number of Rx buffers so that the number of buff-
ers remaining, EmacBlksLeft, is greater than TCPF_LEV.
In Half Duplex Mode, the EMAC jams the Ethernet by sending a continuous
stream of hexadecimal 5s (5fh). When the software frees up the Rx buffers and
the number of buffers remaining, EmacBlksLeft, is greater than TCPF_LEV, the
EMAC stops jamming.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller