EZ80F91MCU Datasheet, PDF (168/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
149
[3:2]
00
OC1_MODE
01
10
11
[1:0]
00
OC0_MODE
01
10
11
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC1_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC0_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
Timer Output Compare Value Register—Low Byte
The Timer3 Output Compare x Value Register—Low Byte, detailed in Table 68,
stores the Low byte of the compare value for OC0–OC3.
Table 68. Compare Value Register—Low Byte
(TMR3_OC0_L = 0082h, TMR3_OC1_L = 0084h,
TMR3_OC2_L = 0086h, TMR3_OC3_L = 0088h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
TMR3_OCx_L
Value Description
00h–FFh These bits represent the Low byte of the 2-byte compare
value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is
bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer compare value.
PS019209-0504
PRELIMINARY
Programmable Reload Timers