EZ80F91MCU Datasheet, PDF (158/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
139
[4:3]
00
CLK_DIV ₀₁
10
11
2
0
TIM_CONT
1
1
0
RLD
1
0
0
TIM_EN
1
System clock divider = 4.
System clock divider = 16.
System clock divider = 64.
System clock divider = 256.
The timer operates in SINGLE PASS mode. TIM_EN (bit 0) is
reset to 0, and counting stops when the end-of-count value is
reached.
The timer operates in CONTINUOUS mode. The timer reload
value is written to the counter when the end-of-count value is
reached.
Reload function is not forced.
Force reload. When a 1 is written to this bit, the values in the
reload registers are loaded into the downcounter.
The programmable reload timer is disabled.
The programmable reload timer is enabled.
Timer Interrupt Enable Register
The Timer x Interrupt Enable Register, detailed in Table 55, is used to control
operation of the timer interrupts. Only bits related to functions present in a given
timer are active.
Table 55. Timer Interrupt Enable
(TMR0_IER = 0061h, TMR1_IER = 0066h, TMR2_IER = 0070h, TMR3_IER = 0075h)
Bit
7
6
Reset
0
0
CPU Access
R/W R/W
Note: R = Read only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
Value
7
0
6
0
IRQ_OC3_EN
1
Description
Unused.
Interrupt requests for OC3 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer
3.
Interrupt requests for OC3 are enabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer
3.
PS019209-0504
PRELIMINARY
Programmable Reload Timers