EZ80F91MCU Datasheet, PDF (374/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
355
Wait State Timing for Read Operations
Figure 68 illustrates the extension of the memory access signals using a single
WAIT state for a Read operation. This wait state is generated by setting CS_WAIT
to 001 in the Chip Select Control Register.
SCLK
T_CLK
T_WAIT
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
RD
INSTRD
Figure 68. Wait State Timing for Read Operations
PS019209-0504
PRELIMINARY
Electrical Characteristics