EZ80F91MCU Datasheet, PDF (215/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
196
UART Line Control Register
This register is used to control the communication control parameters. See
Tables 102 and 103.
Table 102. UART Line Control Registers
(UART0_LCTL = 00C3h, UART1_LCTL = 00D3h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
7
DLAB
6
SB
5
FPE
Value
0
1
0
1
0
1
Description
Access to the UART registers at I/O addresses C0h, C1h,
D0h and D1h is enabled.
Access to the Baud Rate Generator registers at I/O addresses
C0h, C1h, D0h and D1h is enabled.
Do not send a BREAK signal.
Send Break
UART sends continuous zeroes on the transmit output from
the next bit boundary. The transmit data in the transmit shift
register is ignored. After forcing this bit High, the TxD output
is 0 only after the bit boundary is reached. Just before forcing
TxD to 0, the transmit FIFO is cleared. Any new data written
to the transmit FIFO during a break should be written only
after the THRE bit of UARTx_LSR register goes High. This
new data is transmitted after the UART recovers from the
break. After the break is removed, the UART recovers from
the break for the next BRG edge.
Do not force a parity error.
Force a parity error. When this bit and the party enable bit
(pen) are both 1, an incorrect parity bit is transmitted with the
data byte.
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter