EZ80F91MCU Datasheet, PDF (207/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
188
register and determines whether the interrupt occurs due to either an empty
UARTx_THR register or a completed transmission. When the application makes
this determination, it writes the transmit data bytes to the UARTx_THR register.
The number of bytes that the application writes depends on whether or not the
FIFO is enabled. If the FIFO is enabled, the application can write 16 bytes at a
time. If not, the application can write one byte at a time. As a result of the first
Write, the interrupt is deactivated. The CPU then waits for the next interrupt.
When the interrupt is raised by the UART module, the CPU repeats the same pro-
cess until it exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by
writing to the UARTx_MCTL register and reading the UARTx_MCTL register
before starting the process described above.
Receive. The receiver is always enabled, and it continually checks for the start bit
on the RxD input signal. When an interrupt is raised by the UART module, the
application reads the UARTx_IIR register and determines the cause for the inter-
rupt. If the cause is a line status interrupt, the application reads the UARTx_LSR
register, reads the data byte and then can discard the byte or take other appropri-
ate action. If the interrupt is caused by a receive-data-ready condition, the appli-
cation alternately reads the UARTx_LSR and UARTx_RBR registers and
removes all of the received data bytes. It reads the UARTx_LSR register before
reading the UARTx_RBR register to determine that there is no error in the
received data.
To control and check modem status, the application sets up the modem by writing
to the UARTx_MCTL register and reading the UARTx_MSR register before start-
ing the process described above.
Poll Mode Transfers. When interrupts are disabled, all data transfers are referred
to as poll mode transfers. In poll mode transfers, the application must continually
poll the UARTx_LSR register to transmit or receive data without enabling the
interrupts. The same holds true for the UARTx_MSR register. If the interrupts are
not enabled, the data in the UARTx_IIR register cannot be used to determine the
cause of interrupt.
Baud Rate Generator
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and
associated decoding logic. The initial value of the Baud Rate Generator is defined
by the two BRG Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At
the rising edge of each system clock, the BRG decrements until it reaches the
value 0001h. On the next system clock rising edge, the BRG reloads the initial
value from {UARTx_BRG_H, UARTx_BRG_L) and outputs a pulse to indicate the
end-of-count.
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter