EZ80F91MCU Datasheet, PDF (268/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
249
second. Because raw data transfers at this rate consume a certain amount of
CPU bandwidth, the CPU must support traffic from both directions as well as
operate at a minimum clock frequency of (1.25 + 1.25) * 2 = 5 Mhz while transfer-
ring Ethernet packets to and from the physical layer.
Similarly, for 100 BaseT Ethernet, the data rate is 100 Mbits per second, which
equates to 12.5 Mbytes per second. If the eZ80F91 MCU is operating in full duplex
mode over 100 BaseT, the data rate for RX data and TX data is 12.5 Mbytes per
second. Because raw data transfers at this rate consume a certain amount of
CPU bandwidth, the CPU must support traffic from both directions as well as
operate at a minimum clock frequency of (12.5 + 12.5) x 2 = 50 Mhz while trans-
ferring Ethernet packets to and from the physical layer. Consequently, 50 MHz is
the minimum system clock speed that the eZ80^® CPU requires to sustain EMAC
data transfers while not also including any software overhead or additional eZ80^®
tasks.
The FIFO functionality of the EMAC operates at any frequency as long as the user
application avoids overrun and underrun errors via higher-level flow control.
Actual application requirements will dictate Ethernet modes of operation (full-
duplex, half-duplex, etc.). Because each user and application is different, it
becomes the user’s responsibility to control the data flow with these parameters.
Under ideal conditions, the system clock will operate somewhere between 5 MHz
and 50 MHz to handle the EMAC data rates.
EMAC Operation in HALT Modes
When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be
disabled as can other peripherals. Upon receipt of an Ethernet packet, a
maskable Receive interrupt is generated by the EMAC block, just as it would be in
a non-halt mode. Accordingly, the processor wakes up and continues with the
user-defined application.
EMAC Registers
After a system reset, all EMAC registers are set to their default values. Any Writes
to unused registers or register bits are ignored and reads return a value of 0. For
compatibility with future revisions, unused bits within a register should always be
written with a value of 0. Read/Write attributes, reset conditions, and bit descrip-
tions of all of the EMAC registers are provided in this section.
EMAC Test Register
The EMAC Test Register allows test functionality of the EMAC module. Available
test modes are defined for bits [6:0]. See Table 136.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller