EZ80F91MCU Datasheet, PDF (368/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
349
External Memory Read Timing
Figure 64 and Table 236 diagram the timing for external memory reads.
PHI
ADDR[23:0]
T_CLK
T₁
DATA[7:0]
(input)
CSx
MREQ
RD
T₅
T₇
T₉
Figure 64. External Memory Read Timing
T₂
T₃
T₄
T₈
T₈
T₁₀
Table 236. External Memory Read Timing
Parameter Abbreviation
T₁
PHI Clock Rise to ADDR Valid Delay
T₂
PHI Clock Rise to ADDR Hold Time
T₃
Input DATA Valid to PHI Clock Rise Setup Time
T₄
PHI Clock Rise to DATA Hold Time
T₅
PHI Clock Rise to CSx Assertion Delay
T₆
PHI Clock Rise to CSx Deassertion Delay
T₇
PHI Clock Rise to MREQ Assertion Delay
T₈
PHI Clock Rise to MREQ Deassertion Delay
Delay (ns)
Min.
Max.
—
6.8
2.2
—
0.2
—
0.9
—
2.6
10.8
2.4
8.8
2.6
7.0
2.3
6.3
PS019209-0504
PRELIMINARY
Electrical Characteristics