EZ80F91MCU Datasheet, PDF (284/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
265
EMAC MII Management Register
The EMAC MII Management Register is used to control the external PHY
attached to the MII. See Table 154.
Table 154. EMAC MII Management Register
(EMAC_MIIMGT = 003Bh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
7
LCTLD
6
RSTAT
6
SCINC
5
SCAN
4
SPRE
Value
1
0
1
0
1
0
1
0
1
0
Description
Rising edge causes the CTLD control data to be transmitted
to external PHY if MII is not busy. This bit is self clearing.
No operation.
Rising edge causes status to be read from external PHY via
PRSD[15:0] bus if MII is not busy. This bit is self clearing.
No operation.
Scan PHY address increments upon SCAN cycle. The SCAN
bit must also be set for the PHY address to increment after
each scan. The scanning starts at the EmacFiad and
increments up to 1fh. It then rolls back to the EmacFiad
address.
Normal operation.
Perform continuous Read cycles via MII management. While
in scan mode, the EmacIStat[MGTDONE] bit is set when the
current PHY Read has completed. At this time, the EmacPsrd
register holds the Read data and the EmacMIIStat[4:0] holds
the address of the PHY for which the EmacPrsd data pertains.
Normal operation.
Suppress MDO preamble.
Normal preamble.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller