EZ80F91MCU Datasheet, PDF (82/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
63
Table 7. Port x Data Registers
(PA_DR = 0096h, PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)
Bit
7
6
Reset
X
X
CPU Access
R/W R/W
Note: X = Undefined; R/W = Read/Write.
5
X
R/W
4
X
R/W
3
X
R/W
2
X
R/W
1
X
R/W
0
X
R/W
Port x Data Direction Registers
In conjunction with the other GPIO Control Registers, the Port x Data Direction
registers, detailed in Table 8, control the operating modes of the GPIO port pins.
See Table 6 for more information. Px_DDR does not indicate the GPIO direction in
all alternate function modes.
Table 8. Port x Data Direction Registers
(PA_DDR = 0097h, PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Port x Alternate Register 1
In conjunction with the other GPIO Control Registers, the Port x Alternate
Register 1, detailed in Table 9, controls the operating modes of the GPIO port
pins. Px_DDR does not indicate the GPIO direction in all alternate function
modes. See Table 6 for more information.
Table 9. Port x Alternate Registers 1
(PA_ALT1 = 0098h, PB_ALT1 = 009Ch, PC_ALT1 = 00A0h, PD_ALT1 = 00A4h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
PS019209-0504
PRELIMINARY
General-Purpose Input/Output