EZ80F91MCU Datasheet, PDF (76/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
57
Table 5. Clock Peripheral Power-Down Register 2
(CLK_PPD2 = 00DCh)
Bit
7
6
5
4
Reset
0
0
0
0
CPU Access
R/W R
R
R
Note: R = Read Only; R/W = Read/Write.
3
2
1
0
0
0
0
0
R/W R/W R/W R/W
Bit
Position
7
PHI_OFF
[6:4]
3
TIMER3_OFF
2
TIMER2_OFF
1
TIMER1_OFF
0
TIMER0_OFF
Value Description
1
PHI Clock output is disabled (output is high-impedance).
0
PHI Clock output is enabled.
000 Reserved.
1
System clock to TIMER3 is powered down.
0
System clock to TIMER3 is powered up.
1
System clock to TIMER2 is powered down.
0
System clock to TIMER2 is powered up.
1
System clock to TIMER1 is powered down.
0
System clock to TIMER1 is powered up.
1
System clock to TIMER0 is powered down.
0
System clock to TIMER0 is powered up.
PS019209-0504
PRELIMINARY
Low Power Modes