EZ80F91MCU Datasheet, PDF (100/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
81
System Clock
ADDR[23:0]
T1
T2
T_CLK
T3
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 10. Example: Z80 Bus Mode Write Timing
Intel Bus Mode
Chip selects configured for Intel bus mode modify the CPU bus signals to dupli-
cate a four-state memory transfer similar to that found on Intel-style microcontrol-
lers. The bus signals and eZ80F91 pins are mapped as illustrated in Figure 11. In
Intel bus mode, the user can select either multiplexed or nonmultiplexed address
and data buses. In nonmultiplexed operation, the address and data buses are
separate. In multiplexed operation, the lower byte of the address, ADDR[7:0], also
appears on the data bus, DATA[7:0], during State T1 of the Intel bus mode cycle.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States