EZ80F91MCU Datasheet, PDF (163/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
144
Timer Reload Register—High Byte
The Timer x Reload Register—High Byte, detailed in Table 60, stores the most-
significant byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode,
the timer reload value is reloaded into the timer upon end-of-count. When the
reload bit (TMRx_CTL[RLD]) is set to 1, thereby forcing the reload function, the
timer reload value is written to the timer on the next rising edge of the clock.
This register shares its address with the corresponding timer data register.
Table 60. Timer Reload Register—High Byte
(TMR0_RR_H = 0064h, TMR1_RR_H = 0069h, TMR2_RR_H = 0073h,
TMR3_RR_H = 0078h)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
TMR_RR_H
Value Description
00h–FFh These bits represent the High byte of the 2-byte timer
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.
Timer Input Capture Control Register
The Timer x Input Capture Control Register, detailed in Table 61, is used to select
the edge or edges to be captured. For Timer 1, CAP_EDGE_B is used for IC1,
and CAP_EDGE_A is for IC0. For Timer 3, CAP_EDGE_B is for IC3, and
CAP_EDGE_A is for IC2.
Table 61. Timer Input Capture Control Register
(TMR1_CAP_CTL = 006Ah, TMR3_CAP_CTL = 007Bh)
Bit
7
6
Reset
0
0
CPU Access
R/W R/W
Note: R = Read only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:4]
Value
0000
Description
Reserved
PS019209-0504
PRELIMINARY
Programmable Reload Timers