EZ80F91MCU Datasheet, PDF (241/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
222
If a master receiver is involved in a transfer, it must signal the end of the data
stream to the slave transmitter by not generating an ACK on the final byte that is
clocked out of the slave. The slave transmitter must release the data line to allow
the master to generate a STOP or a repeated START condition.
Data Output
by Transmitter
MSB
Data Output
by Receiver
S
1
SCL Signal
from Master
1
2
START Condition
8
9
Clock Pulse for Acknowledge
Figure 45. I²C Acknowledge
Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the
I²C bus. Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I²C
interfaces to the SCL line, meaning that a High-to-Low transition on the SCL line
causes the relevant devices to start counting from their Low period. When a
device clock goes Low, it holds the SCL line in that state until the clock High state
is reached. See Figure 46. The Low-to-High transition of this clock, however, can
not change the state of the SCL line if another clock is still within its Low period.
The SCL line is held Low by the device with the longest Low period. Devices with
shorter Low periods enter a High wait state during this time.
When all devices count off the Low period, the clock line is released and goes
High. There is no difference between the device clocks and the state of the SCL
line; all of the devices start counting the High periods. The first device to complete
its High period again pulls the SCL line Low. In this way, a synchronized SCL
clock is generated with its Low period determined by the device with the longest
clock Low period, and its High period determined by the device with the shortest
clock High period.
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface