EZ80F91MCU Datasheet, PDF (51/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
32
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP BGA
Pin # Pin#
135 D6
Symbol
Rx_ER
Function
MII Receive
Error
Signal Direction
Input
136 C5
Rx_CLK
MII Receive Input
Clock
137 A4
Rx_DV
MII Receive Input
Data Valid
138 E6
RxD0
MII Receive Input
Data
139 B4
RxD1
MII Receive Input
Data
140 D5
RxD2
MII Receive Input
Data
Note: *PHY represents the physical layer of the OSI model.
Description
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Error is provided
by the MII PHY Interface
synchronous to the rising-edge of
Rx_CLK.
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Clock is the Nibble
or Symbol Clock provided by the
MII PHY Interface.
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Data Valid is
provided by the MII PHY Interface
synchronous to the rising-edge of
Rx_CLK.
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Data is provided
by the MII PHY Interface
synchronous to the rising-edge of
Rx_CLK.
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Data is provided
by the MII PHY Interface
synchronous to the rising-edge of
Rx_CLK.
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Data is provided
by the MII PHY Interface
synchronous to the rising-edge of
Rx_CLK.
PS019209-0504
PRELIMINARY
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