EZ80F91MCU Datasheet, PDF (252/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
233
The I²C sends an ACK after receiving the I2C_XSAR byte (the device does not
generate an interrupt at this point). After the next byte of the address (I2C_XSAR)
is received, the I²C generates an interrupt and enters SLAVE mode.Then
I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The
full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 125.
Table 125. I²C Extended Slave Address Register
(I2C_XSAR = 00C9h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
SLAX
Value Description
00h– Least-significant 8 bits of the 10-bit extended slave address.
FFh
I²C Data Register
This register contains the data byte/slave address to be transmitted or the data
byte just received. In TRANSMIT mode, the most-significant bit of the byte is
transmitted first. In RECEIVE mode, the first bit received is placed in the most-sig-
nificant bit of the register. After each byte is transmitted, the I2C_DR register con-
tains the byte that is present on the bus in case a lost arbitration event occurs.
See Table 126.
Table 126. I²C Data Register
(I2C_DR = 00CAh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
DATA
Value Description
00h– I²C data byte.
FFh
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface