EZ80F91MCU Datasheet, PDF (283/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
264
EMAC Hash Table Register
The EMAC Hash Table Register represents the 8x8 hash table matrix. This table
is used as an option to select between different multicast addresses. If a multicast
address is received, the first 6 bits of the CRC are decoded and added to a table
that points to a single bit within the hash table matrix. If the selected bit = 1, the
multicast packet is accepted. If the bit = 0, the multicast packet is rejected. See
Table 153.
Table 153. EMAC Hash Table Register
(EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h, EMAC_HTBL_2 = 0035h,
EMAC_HTBL_3 = 0036h, EMAC_HTBL_4 = 0037h, EMAC_HTBL_5 = 0038h,
EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah)
Bit
EMAC_HTBL_0 Reset
EMAC_HTBL_1 Reset
EMAC_HTBL_2 Reset
EMAC_HTBL_3 Reset
EMAC_HTBL_4 Reset
EMAC_HTBL_5 Reset
EMAC_HTBL_6 Reset
EMAC_HTBL_7 Reset
CPU Access
Note: R/W = Read/Write
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Position
[7:0]
EMAC_HTBL_x
Value
00h–
FFh
Description
This field is the hash table. The 64-bit hash table is
{EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5,
EMAC_HTBL_4, EMAC_HTBL_3, EMAC_HTBL_2,
EMAC_HTBL_1, EMAC_HTBL_0}.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller