EZ80F91MCU Datasheet, PDF (233/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
214
The SPI Data Rate can be calculated using the following equation:
System Clock Frequency
SPI Data Rate (bits/s) =
2 X SPI Baud Rate Generator Divisor
Upon RESET, the 16-bit BRG divisor value resets to 0002h. When the SPI is oper-
ating as a Master, the BRG divisor value must be set to a value of 0003h or
greater. When the SPI is operating as a Slave, the BRG divisor value must be set
to a value of 0004h or greater. A software Write to either the Low- or High-byte
registers for the BRG Divisor Latch causes both the Low and High bytes to load
into the BRG counter, and causes the count to restart.
Data Transfer Procedure with SPI Configured as a Master
The sequence that follows details the procedure for transferring data from a mas-
ter SPI device to a slave SPI device.
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
The external device must deassert the SS pin if currently asserted.
2. Load the SPI Control Register, SPI_CTL.
3. Assert the ENABLE pin of the slave device using a GPIO pin.
4. Load the SPI Transmit Shift Register, SPI_TSR.
5. When the SPI data transfer is complete, deassert the ENABLE pin of the slave
device.
Data Transfer Procedure with SPI Configured as a Slave
The sequence that follows details the procedure for transferring data from a slave
SPI device to a master SPI device.
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while
the SPI slave is currently receiving data.
3. Wait for the external SPI Master device to initiate the data transfer by
asserting SS.
SPI Registers
There are six registers in the Serial Peripheral Interface that provide control, sta-
tus, and data storage functions. The SPI registers are described in the following
paragraphs.
PS019209-0504
PRELIMINARY
Serial Peripheral Interface