EZ80F91MCU Datasheet, PDF (322/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
303
Bit
Position
6
ZDI_BUSAK
[5:0]
Value
0
1
000000
Description
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
Assert the bus acknowledge pin (BUSACK) to pass
control of the address and data buses to an external
peripheral.
Reserved.
Instruction Store 4:0 Registers
The ZDI Instruction Store registers are located in the ZDI Register Write Only
address space. They can be written with instruction data for direct execution by
the CPU. When the ZDI_IS0 register is written, the eZ80F91 device exits the ZDI
break state and executes a single instruction. The Op Codes and operands for the
instruction come from these Instruction Store registers. The Instruction Store Reg-
ister 0 is the first byte fetched, followed by Instruction Store registers 1, 2, 3, and
4, as necessary. Only the bytes the CPU requires to execute the instruction must
be stored in these registers. Some CPU instructions, when combined with the
MEMORY mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to operate.
These 6-byte instructions cannot be executed directly using the ZDI Instruction
Store registers. See Table 194.
Note: The Instruction Store 0 register is located at a higher ZDI address than the other
Instruction Store registers. This feature allows the use of the ZDI auto-address
increment function to load and execute a multibyte instruction with a single data
stream from the ZDI master. Execution of the instruction commences with writing
the final byte to ZDI_IS0.
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface