EZ80F91MCU Datasheet, PDF (164/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
145
[3:2]
00
CAP_EDGE_B ₀₁
10
11
[1:0]
00
CAP_EDGE_A ₀₁
10
11
Disable capture on ICB.
Enable capture only on the falling edge of ICB.
Enable capture only on the rising edge of ICB.
Enable capture on both edges of ICB.
Disable capture on ICA.
Enable capture only on the falling edge of ICA
Enable capture only on the rising edge of ICA.
Enable capture on both edges of ICA.
Timer Input Capture Value A Register—Low Byte
The Timer x Input Capture Value A Register—Low Byte, detailed in Table 62,
stores the Low byte of the capture value for external input A. For Timer 1, the
external input is IC0. For Timer 3, it is IC2.
Table 62. Timer Input Capture Value Register A—Low Byte
(TMR1_CAPA_L = 006Bh, TMR3_CAPA_L = 007Ch)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
Value Description
[7:0]
TMRx_CAPA_L
00h–FFh These bits represent the Low byte of the 2-byte capture
value, {TMRx_CAPA_H[7:0], TMRx_CAPA_L[7:0]}. Bit 7
is bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-
bit timer data value.
PS019209-0504
PRELIMINARY
Programmable Reload Timers