EZ80F91MCU Datasheet, PDF (321/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
302
Table 192. ZDI Read/Write Control Register Functions*
(ZDI_RW_CTL = 16h in the ZDI Register Write Only Address Space) (Continued)
Hex
Value
Command
Hex
Value
Command
09
Reset ADL
ADL ← 0
89
Reserved
0A
Exchange CPU register sets 8A
Reserved
AF ← AF’
BC ← BC’
DE ← DE’
HL ← HL’
0B
Read memory from current 8B
Write memory from current PC
PC value, increment PC
value, increment PC
Note: *The CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. The ZDI
programmer must execute the exchange instruction (EXX) to gain access to the alternate
CPU register set.
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It
enables or disables bus acknowledge in ZDI DEBUG mode and allows ZDI to
force assertion of the BUSACK signal. This register should only be written during
ZDI Debug mode (that is, following a break). See Table 193.
Table 193. ZDI Bus Control Register
(ZDI_BUS_CTL = 17h in the ZDI Register Write Only Address Space)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
Value
7
0
ZDI_BUSAK_EN
1
Description
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK,
is not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface