EZ80F91MCU Datasheet, PDF (154/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
135
The initial value for the OCx pins in OUTPUT COMPARE mode is 0 by default. It
is possible to initialize this value to 1, or force a value at a later time. Setting the
TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state
provided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare
events, the pin stays at the forced value until OCx_MODE is changed. After
release, it retains the forced value until modified by an OUTPUT COMPARE
event.
Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUT-
PUT COMPARE events, and sets output 0 as the master. As a result, outputs 1, 2,
and 3 are caused to disregard output-specific configuration and comparison val-
ues and instead mimic the current settings for output 0.
The OCx bits in the TMR3_IIR register are set whenever the corresponding timer
compares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to gener-
ate a timer interrupt.
Timer Port Pin Allocation
The eZ80F91 device timers interface to the outside world via Ports A and B.
These ports are also used for general purpose I/O as well as other assorted func-
tions. Table 53 lists the timer pins and their respective functions.
Table 53. GPIO Mode Selection When Using Timer Pins
Port
A
GPIO Port GPIO Port
Bits
Mode
PA0
7
PA1
7
PA2
7
PA3
7
PA4
7
PA5
7
PA6
7
PA7
7
Timer Function
PWM_CTL1
MPWM_EN = 0
PWM_CTL1
MPWM_EN = 1
OC0
PWM0
OC1
PWM1
OC2
PWM2
OC3
PWM3
PWM_CTL1
PAIR_EN = 0
PWM_CTL1
PAIR_EN = 1
TOUT0
PWM0
TOUT1
PWM1
EC1
PWM2
PWM3
PS019209-0504
PRELIMINARY
Programmable Reload Timers