EZ80F91MCU Datasheet, PDF (114/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
95
Chip Select x Control Register
The Chip Select x Control register, detailed in Table 28, enables the Chip Selects,
specifies the type of Chip Select, and sets the number of wait states. The reset
state for the Chip Select 0 Control register is E8h, while the reset state for the 3
other Chip Select control registers is 00h.
Table 28. Chip Select x Control Register
(CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)
Bit
7
6
5
4
3
2
1
0
CS0_CTL Reset
1
1
1
0
1
0
0
0
CS1_CTL Reset
0
0
0
0
0
0
0
0
CS2_CTL Reset
0
0
0
0
0
0
0
0
CS3_CTL Reset
0
0
0
0
0
0
0
0
CPU Access
R/W R/W R/W R/W R/W R
R
R
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSX_WAIT
4
CSX_IO
3
CSX_EN
[2:0]
Value Description
000 0 wait states are asserted when this Chip Select is active.
001 1 wait state is asserted when this Chip Select is active.
010 2 wait states are asserted when this Chip Select is active.
011 3 wait states are asserted when this Chip Select is active.
100 4 wait states are asserted when this Chip Select is active.
101 5 wait states are asserted when this Chip Select is active.
110 6 wait states are asserted when this Chip Select is active.
111 7 wait states are asserted when this Chip Select is active.
0
Chip Select is configured as a Memory Chip Select.
1
Chip Select is configured as an I/O Chip Select.
0
Chip Select is disabled.
1
Chip Select is enabled.
000 Reserved.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States