EZ80F91MCU Datasheet, PDF (132/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
113
Flash Control Register
The Flash Control register enables or disables memory access to Flash memory.
I/O access to the Flash control registers and to Flash memory is still possible
while Flash memory space access is disabled.
The minimum access time of internal Flash memory is 60 ns. The Flash Control
Register must be configured to provide the appropriate number of wait states
based on the system clock frequency of the eZ80F91 device. Because the maxi-
mum SCLK frequency is 50 MHZ (20 ns), the default upon RESET is for four wait
states to be inserted for Flash memory access (Flash memory access + one eZ80
Bus Cycle = 60 ns + 20 ns = 80 ns; 80 ns ÷ 20 ns = 4 wait states). See Table 37.
Table 37. Flash Control Register
(FLASH_CTRL = 00F8h)
Bit
7
6
5
4
3
2
1
0
Reset
1
0
0
0
1
0
0
0
CPU Access
R/W R/W R/W R R/W R
R
R
Note: R/W = Read/Write, R = Read Only.
Bit
Position
[7:5]
FLASH_WAIT
[4]
[3]
FLASH_EN
[2:0]
Value Description
000 0 wait states are inserted when the Flash is active.
001 1 wait state is inserted when the Flash is active.
010 2 wait states are inserted when the Flash is active.
011 3 wait states are inserted when the Flash is active.
100 4 wait states are inserted when the Flash is active.
101 5 wait states are inserted when the Flash is active.
110 6 wait states are inserted when the Flash is active.
111 7 wait states are inserted when the Flash is active.
0
Reserved
0
Flash memory access is disabled.
1
Flash memory access is enabled.
000 Reserved
PS019209-0504
PRELIMINARY
Flash Memory