EZ80F91MCU Datasheet, PDF (319/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
300
ZDI Write Data Registers
These three registers are used in the ZDI Write Only register address space to
store the data that is written when a Write instruction is sent to the ZDI Read/Write
Control register (ZDI_RW_CTL). The ZDI Read/Write Control register is located at
ZDI address 16h immediately following the ZDI Write Data registers. As a result,
the ZDI Master is allowed to write the data to {ZDI_WR_U, ZDI_WR_H,
ZDI_WR_L} and the Write command in one data transfer operation. See Table
191.
Table 191. ZDI Write Data Registers
(ZDI_WR_U = 13h, ZDI_WR_H = 14h, and ZDI_WR_L = 15h
in the ZDI Register Write Only Address Space)
Bit
7
6
5
4
3
2
1
0
Reset
X
X
X
X
X
X
X
X
CPU Access
W
W
W
W
W
W
W
W
Note: X = Undefined; W = Write.
Bit
Position
[7:0]
ZDI_WR_L,
ZDI_WR_H,
or
ZDI_WR_L
Value Description
00h–
FFh
These registers contain the data that is written during
execution of a Write operation defined by the
ZDI_RW_CTL register. The 24-bit data value is stored as
{ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than 24 bits
of data are required to complete the required operation,
the data is taken from the least-significant byte(s).
ZDI Read/Write Control Register
The ZDI Read/Write Control register is used in the ZDI Write Only Register
address to read data from, write data to, and manipulate the CPU’s registers or
memory locations. When this register is written, the eZ80F91 device immediately
performs the operation corresponding to the data value written as described in
Table 192. When a Read operation is executed via this register, the requested
data values are placed in the ZDI Read Data registers {ZDI_RD_U, ZDI_RD_H,
ZDI_RD_L}. When a Write operation is executed via this register, the Write data is
taken from the ZDI Write Data registers {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}.
See Table 192. Refer to the eZ80 CPU User Manual (UM0077) on zilog.com for
information regarding the CPU registers.
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface