EZ80F91MCU Datasheet, PDF (280/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
261
EMAC Non-Back-To-Back IPG Register—Part 2
Part 2 of the EMAC Non-Back-To-Back IPG Register is a programmable field rep-
resenting the non-back-to-back interpacket gap. Its default is 12h, which repre-
sents the minimum IPG of 0.96 µs at 100 Mbps or 9.6 µs at 10 Mbps. See Table
149.
Table 149. EMAC Non-Back-To-Back IPG Register—Part 2
(EMAC_IPGR2 = 002Fh)
Bit
7
6
Reset
0
0
CPU Access
R R/W
Note: R = Read Only; R/W = Read/Write
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
Bit
Position
7
[6:0]
IPGR2
Value
0
00h–
7Fh
Description
Reserved.
This is a programmable field representing the non-back-to-
back interpacket gap.
EMAC Maximum Frame Length Register—Low and High Bytes
The 16-bit field resets to 0600h, which represents a maximum Receive frame of
1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged
frame adds four octets for a total of 1522 octets. If a shorter maximum length
restriction is more appropriate, program this field. See Tables 150 and 151.
Note: If a proprietary header is allowed, this field should be adjusted accordingly. For
example, if 12-byte headers are prepended to frames, MAXF should be set to
1524 octets to allow the maximum VLAN tagged frame plus the 12-byte header.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller