EZ80F91MCU Datasheet, PDF (333/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
314
Boundary Scan Cell Functionality
The boundary scan cells implemented are analogous to cell BC_1, defined in the
Standard VHDL Package STD_1149_1_2001.
All boundary scan cells are of the type control-and-observe; they provide both
controllability and observability for the pins to which they are connected. For
tristate outputs and bidirectional pins, this type includes controllability and observ-
ability of output enables.
Chain Sequence and Length
When enabled to shift data, the boundary scan shift register is connected to TDI
at the input line for TRIGOUT and to TDO at PD0. The shift register is arranged so
that data is shifted via the pins starting to the left of the OCI interface pins and pro-
ceeding clockwise around the chip. If a pin features multiple scannable bits (e.g.,
bidirectional pins or tristate output pins), the data is shifted first into the input sig-
nal, then the output, then the output enable (OEN).
The boundary scan register is 213 bits wide. Table 204 shows the ordering of bits
in the shift register, numbering them in clockwise order.
Table 204. Pin to Boundary Scan Cell Mapping
Pin
Direction Scan Cell # Pin
Direction Scan Cell #
TRIGOUT
Input
0
MII_TxD2
Output
107
TRIGOUT
Output
1
MII_TxD3
Output
108
TRIGOUT
OEN
2
MII_COL
Input
109
HALT_SLP
Output
3
MII_CRS
Input
110
BUSACK
Output
4
PA7
Input
111
BUSREQ
Input
5
PA7
Output
112
NMI
Input
6
PA7
OEN
113
RESET
Input
7
PA6
Input
114
RESET_OUT
Output
8
PA6
Output
115
WAIT
Input
9
PA6
OEN
116
INSTRD
Output
10
PA5
Input
117
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
shown to be associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated
with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
PS019209-0504
PRELIMINARY
On-Chip Instrumentation