EZ80F91MCU Datasheet, PDF (250/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
231
received or 78h if the general call address is received. The IFLG bit must be
cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL register is set to 1 then an ACK bit (Low level on
SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR
register contains the two status codes 80h or 90h if SLAVE RECEIVE mode is
entered with the general call address. The received data byte can be read from
the I2C_DR register and the IFLG bit must be cleared to allow the transfer to con-
tinue. If a STOP condition or a repeated START condition is detected after the
acknowledge bit, the IFLG bit is set and the I2C_SR register contains status code
A0h.
If the AAK bit is cleared to 0 during a transfer, the I²C transmits a NACK bit (High
level on SDA) after the next byte is received, and sets the IFLG bit to 1. The
I2C_SR register contains the two status codes 88h or 98h if SLAVE RECEIVE
mode is entered with the general call address. The I²C returns to an idle state
when the IFLG bit is cleared to 0.
I²C Registers
Addressing
The CPU interface provides access to six 8-bit registers: four Read/Write regis-
ters, one Read Only register and two Write Only registers, as indicated in Table
123.
Table 123. I²C Register Descriptions
Register
I2C_SAR
I2C_XSAR
I2C_DR
I2C_CTL
I2C_SR
I2C_CCR
I2C_SRR
Description
Slave address register
Extended slave address register
Data byte register
Control register
Status register (Read Only)
Clock Control register (Write Only)
Software reset register (Write Only)
Resetting the I²C Registers
Hardware Reset. When the I²C is reset by a hardware reset of the eZ80F91
device, the I2C_SAR, I2C_XSAR, I2C_DR, and I2C_CTL registers are cleared to
00h; while the I2C_SR register is set to F8h.
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface