EZ80F91MCU Datasheet, PDF (230/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
211
exchanging a byte of data during a sequence of eight clock cycles. Because SCK
is generated by the master, the SCK pin becomes an input on a slave device. The
SPI contains an internal divide-by-two clock divider. In MASTER mode, the SPI
serial clock is one-half the frequency of the clock signal created by the SPI’s Baud
Rate Generator.
As demonstrated in Figure 41 and Table 111, four possible timing relations can be
chosen by using the clock polarity (CPOL) and CPHA control bits in the SPI Con-
trol register. See the SPI Control Register (SPI_CTL) on page 216. Both the mas-
ter and slave must operate with the identical timing, CPOL, and CPHA. The
master device always places data on the MOSI line a half-cycle before the clock
edge (SCK signal), for the slave device to latch the data.
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Number of Cycles on the SCK Signal
1
2
3
4
5
6
7
8
Sample Input
(CPHA bit = 0) Data Out
MSB
6
5
4
3
2
1
LSB
Sample Input
(CPHA bit = 1) Data Out
ENABLE (To Slave)
Figure 41. SPI Timing
MSB 6
5
4
3
2
1 LSB
Table 111. SPI Clock Phase and Clock Polarity Operation
CPHA
0
0
CPOL
0
1
SCK
Transmit
Edge
Falling
Rising
SCK
Receive
Edge
Rising
Falling
SCK
Idle
State
Low
High
SS High
Between
Characters?
Yes
Yes
PS019209-0504
PRELIMINARY
Serial Peripheral Interface