EZ80F91MCU Datasheet, PDF (298/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
279
Table 174. EMAC PHY Read Status Data Register—High Byte
(EMAC_PRSD_H = 004Fh)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
Value
[7:0]
00h–
EMAC_PRSD_H FFh
Description
These bits represent the High byte of the 2-byte EMAC
PHY Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 15 (msb) of the 16-bit value.
Bit 0 is bit 8 of the 16-bit value.
EMAC MII Status Register
The EMAC MII Status Register is used to determine the current state of the exter-
nal PHY device. See Table 175.
Table 175. EMAC MII Status Register
(EMAC_MIISTAT = 0050h)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
7
BUSY
6
MIILF
Value
1
0
1
0
Description
MII management operation in progress—Busy. This status bit
goes busy whenever the LCTLD (PHY Write) or the RSTAT
(PHY Read) is set in the EMAC_MIIMGT register. It is
negated when the Write or Read operation to the PHY has
completed. In SCAN mode, the BUSY will be asserted until
the SCAN is disabled. Use the EmacIStat[MGTDONE]
interrupt status bit to determine when the data is valid.
Not Busy.
Local copy of PHY Link fail bit.
PHY Link OK.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller