EZ80F91MCU Datasheet, PDF (344/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
325
PLL Control Register 0
The charge pump program, lock detect sensitivity, and system clock source selec-
tions can be set using this register. A brief description of each of these PLL Con-
trol Register 0 attributes is listed below, and further described in Table 207.
Charge Pump Program (CHRP_CTL). Selects one of four values of charge pump
current.
Lock Detect Sensitivity (LDS_CTL). Determines the lock criteria for the PLL.
System Clock Source (CLK_MUX). Selects the system clock source from a choice
of the external crystal oscillator (XTAL), PLL, or Real-Time Clock crystal oscillator.
Table 207. PLL Control Register 0
(PLL_CTL0 = 005Eh)
Bit
7
6
5
Reset
0
0
0
CPU Access
R/W R/W R
Note: R = Read Only; R/W = Read/Write.
4
3
2
1
0
0
0
0
0
0
R R/W R/W R/W R/W
Bit
Position
Value Description
[7:6]
00
CHRP_CTL1 ₀₁
Charge pump current = 100 µA.
Charge pump current = 500 µA.
10 Charge pump current = 1.0mA.
11 Charge pump current = 1.5mA.
[5:4]
00 Reserved.
[3:2]
00
LDS_CTL1
01
Lock criteria—8 consecutive cycles of 20 ns.
Lock criteria—16 consecutive cycles of 20 ns.
10 Lock criteria—8 consecutive cycles of 400ns.
11 Lock criteria—16 consecutive cycles of 400ns.
[1:0]
00 System clock source is the external crystal oscillator.
CLK_MUX
01
System clock source is the PLL.².
10 System clock source is the Real-Time Clock crystal oscillator.
11 Reserved (previous select is preserved).
Notes:
1. Bits can only be programmed when the PLL is disabled. The PLL is disabled when PLL_CTL1
bit 0 is equal to 0.
2. PLL cannot be selected when disabled or out of lock.
PS019209-0504
PRELIMINARY
Phase-Locked Loop