EZ80F91MCU Datasheet, PDF (341/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
322
Lock Detect
The Lock Detect digital block analyzes the PFD output for a locked condition. The
PLL block of the eZ80F91 device is considered locked when the error (or differ-
ence) between the reference clock and divided-down VCO is less than the mini-
mum timing lock criteria for the number of consecutive reference clock cycles. The
lock criteria is selected in the PLL Control Register, PLL_CTL0[LDS_CTL]. When
the locked condition is met, this block outputs a logic High signal (lock) that can
interrupt the CPU.
PLL Normal Operation
By default (after system reset) the PLL is disabled and SCLK = XTAL oscillator.
Assuming the proper loop filter, supply voltages and external oscillator are cor-
rectly configured, the PLL can be enabled. The SCLK/Timer cannot choose the
PLL as its source until the PLL is locked, as determined by the lock detect block.
By forcing the PLL to be locked prior to enabling the PLL as a SCLK/Timer
source, it is assured to be stable and accurate.
The programming flow for normal PLL operation is shown in Figure 61.
PS019209-0504
PRELIMINARY
Phase-Locked Loop