EZ80F91MCU Datasheet, PDF (373/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
354
Table 239. External I/O Write Timing
Delay (ns)
Parameter Abbreviation
Min
Max
T₁
PHI Clock Rise to ADDR Valid Delay
T₂
PHI Clock Rise to ADDR Hold Time
T₃
PHI Clock Fall to Output DATA Valid Delay
T₄
PHI Clock Rise to DATA Hold Time
T₅
PHI Clock Rise to CSx Assertion Delay
T₆
PHI Clock Rise to CSx Deassertion Delay
T₇
PHI Clock Rise to IORQ Assertion Delay
T₈
PHI Clock Rise to IORQ Deassertion Delay
T₉
PHI Clock Fall to WR Assertion Delay
T₁₀
PHI Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
—
6.8
2.2
—
—
7.5
2.3
—
2.6
10.8
2.4
8.8
2.6
7.0
2.3
6.3
1.8
4.5
1.6
4.4
0.4
—
WR Deassertion to DATA Hold Time
0.5
—
WR Deassertion to CSx Hold Time
1.2
—
WR Deassertion to IORQ Hold Time
0.5
—
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to
ADDR, DATA, CSx, or IORQ.
PS019209-0504
PRELIMINARY
Electrical Characteristics