EZ80F91MCU Datasheet, PDF (75/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
56
Table 4. Clock Peripheral Power-Down Register 1
(CLK_PPD1 = 00DBh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
7
GPIO_D_OFF
6
GPIO_C_OFF
5
GPIO_B_OFF
4
GPIO_A_OFF
3
SPI_OFF
2
I2C_OFF
1
UART1_OFF
0
UART0_OFF
Value Description
1
System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
0
System clock to GPIO Port D is powered up.
1
System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
0
System clock to GPIO Port C is powered up.
1
System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
0
System clock to GPIO Port B is powered up.
1
System clock to GPIO Port A is powered down.
Port A alternate functions do not operate correctly.
0
System clock to GPIO Port A is powered up.
1
System clock to SPI is powered down.
0
System clock to SPI is powered up.
1
System clock to I²C is powered down.
0
System clock to I²C is powered up.
1
System clock to UART1 is powered down.
0
System clock to UART1 is powered up.
1
System clock to UART0 and IrDA endec is powered down.
0
System clock to UART0 and IrDA endec is powered up.
PS019209-0504
PRELIMINARY
Low Power Modes