EZ80F91MCU Datasheet, PDF (237/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
218
Table 116. SPI Transmit Shift Register
(SPI_TSR = 00BCh)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
TX_DATA
Value Description
00h– SPI transmit data.
FFh
SPI Receive Buffer Register
The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive
data from the serial bus. The SPIF bit must be cleared prior to a second transfer of
data from the shift register; otherwise, an overrun condition exists. In the event of
an overrun, the byte that causes the overrun is lost.
The SPI Receive Buffer Read Only register shares the same address space as
the SPI Transmit Shift Write Only register. See Table 117.
Table 117. SPI Receive Buffer Register
(SPI_RBR = 00BCh)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
Bit
Position
[7:0]
RX_DATA
Value Description
00h– SPI received data.
FFh
PS019209-0504
PRELIMINARY
Serial Peripheral Interface