EZ80F91MCU Datasheet, PDF (355/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
336
Table 221. Op Code Map—Second Op Code after 0CBh
Legend
Lower Nibble of 2nd Op Code
Upper
Nibble
of Second
Op Code
4
A
RES
4,H
Mnemonic
First Operand
Second Operand
Lower Nibble (Hex)
0
0
RLC
B
1
RL
B
2
SLA
B
3
1
RLC
C
RL
C
SLA
C
2
RLC
D
RL
D
SLA
D
3
RLC
E
RL
E
SLA
E
4
RLC
H
RL
H
SLA
H
5
RLC
L
RL
L
SLA
L
6
RLC
(HL)
RL
(HL)
SLA
(HL)
7
RLC
A
RL
A
SLA
A
8
RRC
B
RR
B
SRA
B
SRL
B
9
RRC
C
RR
C
SRA
C
SRL
C
A
RRC
D
RR
D
SRA
D
SRL
D
B
RRC
E
RR
E
SRA
E
SRL
E
4
BIT
0,B
BIT
0,C
BIT
0,D
BIT
0,E
BIT
0,H
BIT BIT BIT
0,L 0,(HL) 0,A
BIT
1,B
BIT
1,C
BIT
1,D
BIT
1,E
5
BIT
2,B
BIT
2,C
BIT
2,D
BIT
2,E
BIT
2,H
BIT BIT BIT
2,L 2,(HL) 2,A
BIT
3,B
BIT
3,C
BIT
3,D
BIT
3,E
6
BIT
4,B
7
BIT
6,B
8
RES
0,B
9
RES
2,B
A
RES
4,B
BIT
4,C
BIT
6,C
RES
0,C
RES
2,C
RES
4,C
BIT
4,D
BIT
6,D
RES
0,D
RES
2,D
RES
4,D
BIT
4,E
BIT
6,E
RES
0,E
RES
2,E
RES
4,E
BIT
4,H
BIT
6,H
RES
0,H
RES
2,H
RES
4,H
BIT
4,L
BIT
6,L
RES
0,L
RES
2,L
RES
4,L
BIT
4,(HL)
BIT
6,(HL)
RES
0,(HL)
RES
2,(HL)
RES
4,(HL)
BIT
4,A
BIT
6,A
RES
0,A
RES
2,A
RES
4,A
BIT
5,B
BIT
7,B
RES
1,B
RES
3,B
RES
5,B
BIT
5,C
BIT
7,C
RES
1,C
RES
3,C
RES
5,C
BIT
5,D
BIT
7,D
RES
1,D
RES
3,D
RES
5,D
BIT
5,E
BIT
7,E
RES
1,E
RES
3,E
RES
5,E
B
RES
6,B
RES
6,C
RES
6,D
RES
6,E
RES
6,H
RES RES RES
6,L 6,(HL) 6,A
RES
7,B
RES
7,C
RES
7,D
RES
7,E
C
SET
0,B
SET
0,C
SET
0,D
SET
0,E
SET
0,H
SET SET SET
0,L 0,(HL) 0,A
SET
1,B
SET
1,C
SET
1,D
SET
1,E
D
SET
2,B
E
SET
4,B
F
SET
6,B
Notes:
SET SET SET SET SET SET SET SET SET SET SET
2,C 2,D 2,E 2,H 2,L 2,(HL) 2,A 3,B 3,C 3,D 3,E
SET SET SET SET SET SET SET SET SET SET SET
4,C 4,D 4,E 4,H 4,L 4,(HL) 4,A 5,B 5,C 5,D 5,E
SET SET SET SET SET SET SET SET SET SET SET
6,C 6,D 6,E 6,H 6,L 6,(HL) 6,A 7,B 7,C 7,D 7,E
n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
C
RRC
H
RR
H
SRA
H
SRL
H
BIT
1,H
BIT
3,H
BIT
5,H
BIT
7,H
RES
1,H
RES
3,H
RES
5,H
RES
7,H
SET
1,H
SET
3,H
SET
5,H
SET
7,H
D
RRC
L
RR
L
SRA
L
SRL
L
BIT
1,L
BIT
3,L
BIT
5,L
BIT
7,L
RES
1,L
RES
3,L
RES
5,L
RES
7,L
SET
1,L
SET
3,L
SET
5,L
SET
7,L
E
RRC
(HL)
RR
(HL)
SRA
(HL)
SRL
(HL)
BIT
1,(HL)
BIT
3,(HL)
BIT
5,(HL)
BIT
7,(HL)
RES
1,(HL)
RES
3,(HL)
RES
5,(HL)
RES
7,(HL)
SET
1,(HL)
SET
3,(HL)
SET
5,(HL)
SET
7,(HL)
F
RRC
A
RR
A
SRA
A
SRL
A
BIT
1,A
BIT
3,A
BIT
5,A
BIT
7,A
RES
1,A
RES
3,A
RES
5,A
RES
7,A
SET
1,A
SET
3,A
SET
5,A
SET
7,A
PS019209-0504
PRELIMINARY
Op-Code Map