EZ80F91MCU Datasheet, PDF (55/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
36
Table 3. Register Map (Continued)
Address
(hex) Mnemonic
Name
Reset
CPU Page
(hex) Access #
Ethernet Media Access Controller
0020 EMAC_TEST
EMAC Test Register
00
R/W 249
0021 EMAC_CFG1
EMAC Configuration Register
00
R/W 251
0022 EMAC_CFG2
EMAC Configuration Register
37
R/W 253
0023 EMAC_CFG3
EMAC Configuration Register
0F
R/W 254
0024 EMAC_CFG4
EMAC Configuration Register
00
R/W 255
0025 EMAC_STAD_0
EMAC Station Address—Byte 0
00
R/W 256
0026 EMAC_STAD_1
EMAC Station Address—Byte 1
00
R/W 256
0027 EMAC_STAD_2
EMAC Station Address—Byte 2
00
R/W 256
0028 EMAC_STAD_3
EMAC Station Address—Byte 3
00
R/W 256
0029 EMAC_STAD_4
EMAC Station Address—Byte 4
00
R/W 256
002A EMAC_STAD_5
EMAC Station Address—Byte 5
00
R/W 256
002B EMAC_TPTV_L
EMAC Transmit Pause Timer Value—
00
Low Byte
R/W 257
002C EMAC_TPTV_H
002D
002E
002F
0030
EMAC_IPGT
EMAC_IPGR1
EMAC_IPGR2
EMAC_MAXF_L
EMAC Transmit Pause Timer Value—
00
High Byte
EMAC Inter-Packet Gap
15
EMAC Non-Back-Back IPG
0C
EMAC Non-Back-Back IPG
12
EMAC Maximum Frame Length—Low
00
Byte
R/W 257
R/W 258
R/W 260
R/W 261
R/W 261
0031 EMAC_MAXF_H EMAC Maximum Frame Length—High 06
Byte
R/W 262
0032 EMAC_AFR
EMAC Address Filter Register
00
R/W 263
0033 EMAC_HTBL_0
EMAC Hash Table—Byte 0
00
R/W 264
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read Only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a
an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.
5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
PS019209-0504
PRELIMINARY
Register Map