EZ80F91MCU Datasheet, PDF (81/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
62
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port
pin is tristated. If the pin receives the correct edge from an external device, the
port pin generates an interrupt request signal to the CPU. Any time a port pin is
configured for an edge-triggered interrupt, writing a 1 to that pin’s Port x Data reg-
ister causes a reset of an edge-detected interrupt. The programmer must set the
bit in the Port x Data register to 1 before entering either single or dual edge-trig-
gered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a
rising and a falling edge on the pin cause an interrupt request to be sent to the
CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the
value in the Port x Data register determines if a positive or negative edge causes
an interrupt request. A 0 in the Port x Data register bit sets the selected pin to gen-
erate an interrupt request for falling edges. A 1 in the Port x Data register bit sets
the selected pin to generate an interrupt request for rising edges.
GPIO Control Registers
The 16 GPIO Control Registers operate in groups of four with a set for each Port
(A, B, C, and D). Each GPIO port features a Port Data register, Port Data Direc-
tion register, Port Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to
the Port x Data registers, detailed in Table 7, is driven on the corresponding pins.
In all modes, reading from the Port x Data registers always returns the current
sampled value of the corresponding pins. When the port pins are configured as
edge-triggered interrupt sources, writing a 1 to the corresponding bit in the Port x
Data register clears the interrupt signal that is sent to the CPU. When the port pins
are configured for edge-selectable interrupts or level-sensitive interrupts, the
value written to the Port x Data register bit selects the interrupt edge or interrupt
level. See Table 6 for more information.
PS019209-0504
PRELIMINARY
General-Purpose Input/Output