EZ80F91MCU Datasheet, PDF (301/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
282
EMAC Transmit Read Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Transmit Read Pointer Register are always zero. See Table 179.
Table 179. EMAC Transmit Read Pointer Register—High Byte
(EMAC_TRP_H = 0054h)
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
CPU Access
RO RO RO RO RO RO RO RO
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_TRP_H
Value
00h–
1Fh
Description
These bits represent the High byte of the 2-byte EMAC
TxDMA Transmit Read Pointer value, {EMAC_TRP_H,
EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit
0 is bit 8 of the 16-bit value.
EMAC Receive Blocks Left Register—Low and High Bytes
This register reports the number of buffers left in the Receive EMAC shared mem-
ory. The hardware uses this information, along with the Block-Level set in the
EMAC_BUFSZ register, to determine when to transmit a pause control frame.
Software can use this information to determine when it should request that a
pause control frame be transmitted (by setting bit 6 of the EMAC_CFG4 register).
For the BlksLeft logic to operate properly, the Receive buffer must contain at least
one more packet buffer than the number of packet buffers required for the largest
packet. That is, one packet cannot fill the entire Receive buffer. Otherwise, the
BlksLeft will be in error. See Tables 180 and 181.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller