EZ80F91MCU Datasheet, PDF (316/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
297
ZDI Break Control Register
The ZDI Break Control register is used to enable break points. ZDI asserts a
break when the CPU instruction address, ADDR[23:0], matches the value in the
ZDI Address Match 3 registers, {ZDI_ADDR3_U, ZDI_ADDR3_H,
ZDI_ADDR3_L}. BREAKs can only occur on an instruction boundary. If the
instruction address is not the beginning of an instruction (that is, for multibyte
instructions), then the break occurs at the end of the current instruction. The
BRK_NEXT bit is set to 1. The BRK_NEXT bit must be reset to 0 to release the
break. See Table 189.
Table 189. ZDI Break Control Register
(ZDI_BRK_CTL = 10h in the ZDI Write Only Register Address Space)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
7
BRK_NEXT
6
BRK_ADDR3
5
BRK_ADDR2
Value Description
0
The ZDI break on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
1
The ZDI break on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. Break points only occur on the first Op Code in
a multibyte Op Code instruction. If the ZCL pin is High and
the ZDA pin is Low at the end of RESET, this bit is set to 1
and a break occurs on the first instruction following the
RESET. This bit is set automatically during ZDI break on
address match. A break can also be forced by writing a 1
to this bit.
0
The ZDI break, upon matching break address 3, is
disabled.
1
The ZDI break, upon matching break address 3, is
enabled.
0
The ZDI break, upon matching break address 2, is
disabled.
1
The ZDI break, upon matching break address 2, is
enabled.
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface