EZ80F91MCU Datasheet, PDF (77/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
58
General-Purpose Input/Output
GPIO Overview
The eZ80F91 device features 32 General-Purpose Input/Output (GPIO) pins. The
GPIO pins are assembled as four 8-bit ports— Port A, Port B, Port C, and Port D.
All port signals can be configured for use as either inputs or outputs. In addition,
all of the port pins can be used as vectored interrupt sources for the CPU.
The eZ80F91 microcontroller’s GPIO ports are slightly modified from its eZ80^®
predecessors. Specifically, Port A pins now can source 8 mA and sink 10 mA. In
addition, the Port B and C inputs now feature Schmitt-trigger input buffers.
GPIO Operation
GPIO operation is the same for all four GPIO ports (Ports A, B, C, and D). Each
port features eight GPIO port pins. The operating mode for each pin is controlled
by four bits that are divided between four 8-bit registers. These GPIO mode con-
trol registers are:
• Port x Data Register (Px_DR)
• Port x Data Direction Register (Px_DDR)
• Port x Alternate Register 1 (Px_ALT1)
• Port x Alternate Register 2 (Px_ALT2)
where x can be A, B, C, or D representing any of the four GPIO ports A, B, C, or D.
The mode for each pin is controlled by setting each register bit pertinent to the pin
to be configured. For example, the operating mode for Port B Pin 7 (PB7) is set by
the values contained in PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of
each port pin for nine modes. In all modes, reading of the Port x Data register
returns the sampled state, or level, of the signal on the corresponding pin. Table 6
indicates the function of each port signal based upon these four register bits. After
a RESET event, all GPIO port pins are configured as standard digital inputs
(GPIO Mode 2), with interrupts disabled.
PS019209-0504
PRELIMINARY
General-Purpose Input/Output