EZ80F91MCU Datasheet, PDF (372/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
353
Table 238. External I/O Read Timing (Continued)
Parameter Abbreviation
T₈
PHI Clock Rise to IORQ Deassertion Delay
T₉
PHI Clock Rise to RD Assertion Delay
T₁₀
PHI Clock Rise to RD Deassertion Delay
Delay (ns)
Min
2.3
2.7
2.4
Max
6.3
7.0
6.3
External I/O Write Timing
Figure 67 and Table 239 diagram the timing for external I/O Writes. PHI clock rise/
fall to signal transition timing is independent of the particular bus mode employed
(eZ80, Z80, Intel, or Motorola).
T_CLK
PHI
ADDR[23:0]
DATA[7:0]
(output)
CSx
IORQ
WR
T₁
T₅
T₇
T₃
T₉
Figure 67. External I/O Write Timing
T₂
T₄
T₆
T₈
T₁₀
PS019209-0504
PRELIMINARY
Electrical Characteristics