EZ80F91MCU Datasheet, PDF (25/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
6
Pin Characteristics
Table 2 describes the pins and functions of the eZ80F91 MCU’s 144-pin LQFP
package and 144-ball BGA package.
Table 2. Pin Identification on the eZ80F91 Device
LQFP BGA
Pin # Pin#
1
A1
Symbol
ADDR0
Function
Signal Direction
Address Bus Bidirectional
2
B1
ADDR1 Address Bus Bidirectional
3
B2
ADDR2 Address Bus Bidirectional
4
C3
ADDR3 Address Bus Bidirectional
Note: *PHY represents the physical layer of the OSI model.
Description
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
PS019209-0504
PRELIMINARY
Architectural Overview