EZ80F91MCU Datasheet, PDF (370/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
351
Table 237. External Memory Write Timing
Delay (ns)
Parameter Abbreviation
Min.
Max.
T₁
PHI Clock Rise to ADDR Valid Delay
—
6.8
T₂
PHI Clock Rise to ADDR Hold Time
2.2
—
T₃
PHI Clock Fall to Output DATA Valid Delay
—
7.5
T₄
PHI Clock Rise to DATA Hold Time
2.3
—
T₅
PHI Clock Rise to CSx Assertion Delay
2.6
10.8
T₆
PHI Clock Rise to CSx Deassertion Delay
2.4
8.8
T₇
PHI Clock Rise to MREQ Assertion Delay
2.6
7.0
T₈
PHI Clock Rise to MREQ Deassertion Delay
2.3
6.3
T₉
PHI Clock Fall to WR Assertion Delay
1.8
4.5
T₁₀
PHI Clock Rise to WR Deassertion Delay*
1.6
4.4
WR Deassertion to ADDR Hold Time
0.4
—
WR Deassertion to DATA Hold Time
0.5
—
WR Deassertion to CSx Hold Time
1.2
—
WR Deassertion to MREQ Hold Time
0.5
—
* At the conclusion of a Write cycle, deassertion of WR always occurs before any
change to ADDR, DATA, CSx, or MREQ.
PS019209-0504
PRELIMINARY
Electrical Characteristics