EZ80F91MCU Datasheet, PDF (171/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
152
The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally
enabled by setting TMR3_PWM_CTL1[PAIR_EN] to 1. The individual PWM gen-
erators must be enabled for the associated inverted PWM signals to be output.
For each of the 4 PWM generators, there is a 16-bit rising edge value
{TMR3_PWMxR_H[PWMxR_H], TMR3_PWMxR_L[PWMxR_L]} and a 16-bit fall-
ing edge value {TMR3_PWMxF_H[PWMxF_H], TMR3_PWMxF_L[PWMxF_L]} for
a total of 16 registers. The rising-edge byte pairs define the timer count at which
the PWMx output transitions from Low to High. Conversely, the falling-edge byte
pairs define the timer count at which the PWMx output transitions from High to
Low. Upon reset, all enabled PWM outputs begin Low and all PWMx outputs
begin High. When the PWMx output is Low, the logic is looking for a match
between the timer count and the rising edge value, and vice versa. Therefore, in a
case in which the rising edge value is the same as the falling edge value, the
PWM output frequency is one-half the rate at which the counter passes through its
entire count cycle (from reload value down to 0000h).
Figures 30 and 31 demonstrate a simple multi-PWM output and an expanded
view of the timing, respectively. Associated control values are listed in Table 71.
T3 Count
PWM0
0 CBA9 8 7 6 5 4 3 2 1CBA9 8 7 6 5 4 3 2 1CBA9 8 7 6 5 4 3 2 1CBA
PWM0
PWM1
PWM1
Figure 30. Multi-PWM Operation
System Clock
Clock Enable
T3 Count
A
9
8
7
Figure 31. Multi-PWM Operation—Expanded View of Timing
6
5
4
PS019209-0504
PRELIMINARY
Programmable Reload Timers