EZ80F91MCU Datasheet, PDF (28/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
9
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP BGA
Pin # Pin#
17 F1
Symbol
ADDR12
Function
Signal Direction
Address Bus Bidirectional
18 F2
ADDR13 Address Bus Bidirectional
19 F3
ADDR14 Address Bus Bidirectional
20 F4
ADDR15 Address Bus Bidirectional
Note: *PHY represents the physical layer of the OSI model.
Description
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
PS019209-0504
PRELIMINARY
Architectural Overview