EZ80F91MCU Datasheet, PDF (306/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
287
downloads and uploads data, with a maximum frequency of one-half the eZ80F91
system clock frequency, or less. See Table 185 for recommended values.
Table 185. Recommend ZDI Clock vs. System Clock Frequency
System Clock Frequency
3–10 MHz
8–16 MHz
12–24 MHz
20–50 MHz
ZDI Clock Frequency
1 MHz
2 MHz
4 MHz
8 MHz
ZDI-Supported Protocol
ZDI supports a bidirectional serial protocol. The protocol defines any device that
sends data as the transmitter and any receiving device as the receiver. The
device controlling the transfer is the master and the device being controlled is the
slave. The master always initiates the data transfers and provides the clock for
both receive and transmit operations. The ZDI block on the eZ80F91 device is
considered a slave in all data transfers.
Figure 52 illustrates the schematic for building a connector on a target board. This
connector allows the user to connect directly to the ZPAK emulator using a six-pin
header.
TV_DD
(Target V_DD)
330 KΩ
330 KΩ
eZ80F91
TCK (ZCL)
TDI (ZDA)
21
43
65
6-Pin Target Connector
Figure 52. Schematic For Building a Target Board ZPAK Connector
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface