EZ80F91MCU Datasheet, PDF (276/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
257
EMAC Transmit Pause Timer Value Register—Low and High Bytes
The Low and High bytes of the EMAC Transmit Pause Timer Value Register are
inserted into outgoing pause control frames. See Tables 143 and 144.
Table 143. EMAC Transmit Pause Timer Value Register—Low Byte
(EMAC_TPTV_L = 002Bh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Position
Value
[7:0]
00h–
EMAC_TPTV_L FFh
Description
The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.
Table 144. EMAC Transmit Pause Timer Value Register—High Byte
(EMAC_TPTV_H = 002Ch)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Position
Value
[7:0]
00h–
EMAC_TPTV_H FFh
Description
The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller