EZ80F91MCU Datasheet, PDF (285/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
266
Bit
Position
[2:0]
CLKS
Value Description
Programmable divisor that produces MDC from SCLK.
000 MDC = SCLK ÷ 4.
001 MDC = SCLK ÷ 4.
010 MDC = SCLK ÷ 6.
011 MDC = SCLK ÷ 8.
100 MDC = SCLK ÷ 10.
101 MDC = SCLK ÷ 14.
110 MDC = SCLK ÷ 20.
111 MDC = SCLK ÷ 28.
EMAC PHY Configuration Data Register—Low Byte
The Low Byte of the EMAC PHY Configuration Data Register represents the con-
figuration data written to the external PHY. See Table 155.
Table 155. EMAC PHY Configuration Data Register—Low Byte
(EMAC_CTLD_L = 003Ch)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
Value
[7:0]
00h–
EMAC_CTLD_L FFh
Description
These bits represent the Low byte of the 2-byte PHY
configuration data value, {EMAC_CTLD_H,
EMAC_CTLD_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit
0 (lsb) of the 16-bit value.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller