EZ80F91MCU Datasheet, PDF (30/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
11
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP BGA
Pin # Pin#
27 G4
Symbol
ADDR20
Function
Signal Direction
Address Bus Bidirectional
28 H3
ADDR21 Address Bus Bidirectional
29 J1
ADDR22 Address Bus Bidirectional
30 G5
ADDR23 Address Bus Bidirectional
31 J2
32 H4
33 J3
V_DD
V_SS
CS0
Power Supply
Ground
Chip Select 0 Output, Active Low
Note: *PHY represents the physical layer of the OSI model.
Description
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Power Supply.
Ground.
CS0 Low indicates that an access
is occurring in the defined CS0
memory or I/O address space.
PS019209-0504
PRELIMINARY
Architectural Overview